A thin film transistor liquid crystal display (“TFTLCD”) device in the art generally includes a drive circuit and an array of cells driven by the drive circuit. The drive circuit may further include a plurality of gate lines formed in parallel to each other and a plurality of source lines formed orthogonal to the gate lines. Each of the cells, disposed near an intersection of one of the gate lines and one of the source lines, includes a thin film transistor (“TFT”) and a storage capacitor (CS). The TFT further includes a gate coupled to a corresponding gate line and a source terminal coupled to a corresponding source line. A CS-on-gate type TFT in the art refers to a TFT to which a corresponding CS is formed between a source terminal of the TFT and a previous gate line.
FIG. 1A is a schematic diagram of a CS-on-gate type TFTLCD 10 in the art. An exemplary cell 12 of TFTLCD 10 includes a TFT 14 and a storage capacitor 16. TFT 14 includes a gate 14-2 coupled to an n-th gate line Gn, a drain terminal 14-4 coupled to an m-th source line Sm, and a source terminal 14-6 which serves as one electrode of storage capacitor 16. The source and drain are interchangeable in a TFT. The other electrode 16-2 of storage capacitor 16 is coupled to a previous gate line Gn-1. Cell 12 may further include another capacitor 18 formed between source terminal 14-6 and a common electrode (not numbered).
FIGS. 1B and 1C are waveform diagrams of TFTLCD 10 shown in FIG. 1A. Referring to FIG. 1C, when the gate line Gn-1 is selected, i.e., V(Gn-1) is logically high, the potential of source terminal 14-6 or V16 is pulled high from a reference voltage level. When the selection period of the gate line Gn-1 is concluded and V(Gn-1) becomes logically low, V16 is pulled low to the reference voltage level. Next, when the gate line Gn is selected and V(Gn) is logically high, storage capacitor 16 is charged from the reference voltage level to the peak value of a source signal V(Sm) transmitted via source line Sm. It is assumed that the source signal V(Sm) is provided in line inversion or dot inversion. In driving an LCD device with line inversion, the polarity of a source signal is inverted every line of the gates during a frame time. In driving an LCD device with dot inversion, the polarity of a source signal is inverted every line of sources during a frame time. The source signal V(Sm) and the gate signals V(Gn-1) and V(Gn) are synchronized by a timing controller (not shown) of TFTLCD 10. When the selection period of the gate line Gn is concluded and V(Gn) becomes logically low, storage capacitor 16 is slightly discharged from the peak value due to a feed-through effect. A feed-through effect is a phenomenon that a voltage applied to a TFT is shifted to a negative polarity voltage when the TFT is turned off from the on state. If the feed-through voltage ΔV becomes great, there arises a problem that a remarkable image flicker occurs.
FIG. 2A is a schematic diagram of another CS-on-gate type TFTLCD 30 in the art. An exemplary cell 32 of TFTLCD 30 includes a first TFT 34, a second TFT 38 and a storage capacitor 36. First TFT 34 includes a gate 34-2 coupled to an n-th gate line Gn, a drain terminal 34-4 coupled to an m-th source line Sm, and a source terminal 34-6 which serves as one electrode of storage capacitor 36. Second TFT 38 includes a gate 38-2 coupled to an (n-1)-th gate line Gn-1, a drain terminal 38-4 coupled to an m-th source line Sm, and a source terminal (not numbered) coupled to source terminal 34-6 of first TFT 34. The other electrode 36-2 of storage capacitor 36 is coupled to the gate line Gn-1. Cell 32 may further include another capacitor 40 formed between source terminal 34-6 and a common electrode (not numbered).
FIGS. 2B and 2C are waveform diagrams of TFTLCD 30 shown in FIG. 2A. Referring to FIG. 2C, when the gate line Gn-1 is selected and V(Gn-1) is logically high, the potential of source terminal 34-6 is pulled high from a reference voltage level, and then pulled low when second TFT 38 is turned on by the gate signal V(Gn-1). When the selection period of the gate line Gn-1 is concluded and V(Gn-1) becomes logically low, V36 is pulled low to a negative voltage level. Next, when the gate line Gn is selected and V(Gn) is logically high, storage capacitor 36 is charged from the negative voltage level to the peak value of a source signal V(Sm) transmitted via source line Sm. When the selection period of the gate line Gn is concluded and V(Gn) becomes logically low, storage capacitor 36 is slightly discharged from the peak value due to the feed-through effect. Referring to FIGS. 1B and 2B, it is more difficult to charge cell 32 than cell 12 of FIG. 1A in line inversion or dot inversion.
It is thus desirable to have a drive circuit and a drive method to alleviate the feed-through effect.